NPU Controller Modules¶

RTL source on GitHub

SystemVerilog sources documented on this page:

hw/rtl/NPU_Controller/npu_controller_top.sv — View on GitHub
hw/rtl/NPU_Controller/NPU_Control_Unit/ctrl_npu_decoder.sv — View on GitHub
hw/rtl/NPU_Controller/Global_Scheduler.sv — View on GitHub

1. Controller Top¶

npu_controller_top.sv integrates the AXI-Lite frontend, instruction decoder, and global scheduler into a single controller boundary.

2. Instruction Decoder¶

ctrl_npu_decoder.sv parses the 64-bit VLIW instruction word: strips the 4-bit opcode and routes the 60-bit body into the appropriate typed struct (GEMV_op_x64_t, memcpy_op_x64_t, etc.).

3. Global Scheduler¶

Global_Scheduler.sv receives decoded instruction fields, emits per-core control μops, tracks in-flight async instructions, maintains the dependency scoreboard, and gates new dispatches when a hazard is detected.

Last verified against

Current public pccx-FPGA-NPU-LLM-kv260 main clone used by the documentation CI. Controller source references should stay aligned with files present in that public RTL tree.