ISA Type Package

RTL source on GitHub

SystemVerilog source documented on this page: hw/rtl/NPU_Controller/NPU_Control_Unit/ISA_PACKAGE/isa_pkg.sv

View on GitHub →

isa_pkg.sv is the single source of truth for all instruction types, opcode enums, and micro-op structs. Every RTL module does import isa_pkg::*; — no header includes are needed downstream.

The package is organized in compilation order:

  1. Basic address and control typedefs

  2. Device-direction enums (from_device_e, to_device_e, async_e)

  3. GEMV/GEMM flags struct

  4. Opcode enum (opcode_e)

  5. Per-instruction encoding structs (60-bit bodies)

  6. CVO function codes and flags

  7. Memory routing enums (data_route_e)

  8. Micro-op structs decoded from each instruction

Encoding-table headers

Three companion .svh files sit next to isa_pkg.sv and define the bit-layout tables the host driver mirrors:

  • isa_x32.svh — 32-bit field layouts (legacy + control-plane opcodes).

  • isa_x64.svh — 64-bit VLIW field layouts (the active opcode set).

  • isa_memctrl.svh — memory-controller opcode bodies (MEMSET / LOAD / STORE / CVO).

The host C driver’s uCA_v1_api.h claims its bit layout matches isa_x64.svh opcode-by-opcode; whenever a field width changes the SV header and the driver header must move together.

Last verified against

Commit 8c09e5e @ pccxai/pccx-FPGA-NPU-LLM-kv260 (2026-04-29).

See also

Instruction Encoding — human-readable description of the same encoding. Per-Instruction Encoding — per-instruction field tables.